Integrated electronic circuit incorporating a capacitor

ABSTRACT

A non-volatile memory element includes a transistor for selecting the element and a capacitor for recording a binary value by electrical breakdown of an insulating layer of the capacitor. A structure of the memory element is modified in order to allow a higher degree of integration of the element within an electronic circuit of the MOS type. In addition, the memory element is made more robust with respect to a high electrical voltage (VDD) used for recording the binary value. The transistor includes a drain in the substrate with electric field drift in a longitudinal direction extending towards the capacitor. The electric field drift region for the drain includes a first extension underneath the gate of the transistor opposite the source and a second extension underneath the insulating layer of the capacitor. Doping of the substrate for the electric field drift region is limited to a region substantially corresponding to a distance between the gate and an electrode of the capacitor.

PRIORITY CLAIM

The present application is a divisional of U.S. application Ser. No.11/600,584 filed Nov. 15, 2006 which claims priority from French PatentApplication No. 05 11775 filed Nov. 21, 2005, the disclosures of whichare hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

The present invention relates to a non-volatile memory element, and alsoto a fabrication process for such a memory element.

2. Description of Related Art

A known technique is to fabricate a non-volatile memory element in theform of an integrated electronic circuit of the MOS (forMetal-Oxide-Semiconductor) type, in which a value of one bit is recordedby electrical breakdown of an insulating layer of a capacitor. Thebinary value is then stored permanently. Such non-volatile memoryelements are useful, for example, for repairing static or dynamic randomaccess memories having high storage capacities.

The binary value 1 is recorded in such a non-volatile memory element byselecting the memory element by means of a gate voltage of an MOStransistor connected in series with the capacitor. A high electricalvoltage, of around 7 V (volts), is then applied between power supplyterminals of the element, so as to cause the breakdown of the insulatinglayer of the capacitor. The capacitor thus becomes electricallyconducting. Such an operation is sometimes referred to as ‘antifuse’.

During a later operation for reading the binary value stored in thenon-volatile memory element, the memory element is supplied with avoltage of around 2.5 V, in accordance with the normal power supplystandards for integrated circuits of the MOS type. The memory element isagain selected by the gate voltage of the transistor connected to thecapacitor, and the conducting or insulating state of the capacitor isdetected in order to read the binary value stored.

In order to obtain low-cost non-volatile memory elements, these arefabricated according to the normal fabrication processes for integratedcircuits of the MOS type, which are designed to operate with a powersupply voltage of around 2.5 V. The structure of the transistorconnected to the capacitor of each non-volatile memory element thenneeds to be designed so that this transistor is not damaged by the highelectrical voltage used to record a binary value equal to 1.

For this purpose, U.S. Pat. No. 6,421,293 (EP 1,014,447) discloses anon-volatile memory element, using CMOS technology, in which thetransistor of the memory element comprises a drain region with electricfield drift. Such a transistor is widely denoted as a ‘drift-MOSFET’transistor. It allows a high electrical voltage to be applied to thememory element for recording the binary value 1, without damaging thetransistor. The reason for this is that part of the high electricalvoltage is consumed in the drain region by ohmic resistive effect, afterthe breakdown of the insulating layer of the capacitor.

However, in a memory element such as is disclosed in aforementionedpatent, the drift-field drain region of the transistor and the capacitorare formed within an n-doped well. In addition, this well comprises anelectrical isolation region of the STI (for Shallow Trench Isolation)type. The design rules that are necessarily used for the formation of adoping well impose that alignment margins be adhered to, notably becauseof the implementation of lithographic process steps. The non-volatilememory element then occupies a portion of surface of an integratedelectronic circuit substrate that is significant, typically of around 10μm² (square micrometers). It is not therefore possible to substantiallyincrease the integration level of the non-volatile memory element, forexample in order to reduce its cost price.

A need accordingly exists for a non-volatile memory element that may befabricated using MOS technology and that is compatible with a high levelof integration.

SUMMARY OF THE INVENTION

To address the foregoing need, a non-volatile memory element for thestorage of one bit comprises a capacitor for recording a value of thebit by electrical breakdown of an insulating layer of the capacitor anda transistor for selecting this element. The transistor and thecapacitor are formed within an active region of an integrated electroniccircuit substrate. The transistor is of the field-effect MOS type. Thetransistor incorporates a source region designed to be connected to afirst power supply terminal for the memory element, a gate designed tobe connected to a selection terminal for the memory element, and a drainregion with electric field drift in a longitudinal direction. Thecapacitor incorporates the insulating layer, which is disposed on top ofa surface of the substrate, a first electrode, which is disposed on theinsulating layer and which is designed to be connected to a second powersupply terminal for the memory element, and a second electrode. Thissecond electrode comprises a first portion of the substrate that issituated under the insulating layer and within the extension of thedrain region of the transistor on a side opposite to the gate. Accordingto an embodiment, the drift-field drain region comprises a secondportion of the substrate within the active region, whose doping islimited to an interval substantially corresponding to a distance betweenthe gate of the transistor and the first electrode parallel to thelongitudinal direction.

Given that the gate of the transistor and the first electrode of thecapacitor are two structures in relief above the surface of thesubstrate, they can be used to bound the second portion of the substratein which the doping of the drain region is effected. Such a doping canbe carried out by scanning the surface of the substrate with a dopantspecies implantation beam. During the scanning, the portion of thesubstrate into which the dopant species penetrate is bounded by thestructures in relief of the gate of the transistor and of the firstelectrode of the capacitor. These structures in relief stop the dopantspecies of the beam before they reach the surface of the substrate. Inthe jargon of those skilled in the art, the drift-field drain region issaid to be self-aligned relative to the gate of the transistor and tothe capacitor. Such a self-alignment allows alignment margins to beeliminated and the level of integration of the non-volatile memoryelement to be increased. In particular, a non-volatile memory elementaccording to the invention can occupy a part of the substrate surfacethat is less than 7 μm², or even less than 3 μm².

Such a doping with self-alignment, which is used to form the drift-fielddrain region, is advantageously carried out at the same time as thedoping of extensions of source and of drain regions of MOS transistorsof an integrated electronic circuit incorporating the non-volatilememory element. Such extensions are portions of the substrate that aresituated underneath lateral sides of MOS gate structures, at the ends ofthe associated channels. They are usually referred to as LLDs, forLightly Doped Drains.

Preferably, the first electrode and the insulating layer of thecapacitor can have a MOS transistor gate structure. They can then beformed at the same time as the gates of MOS transistors of the circuit,and notably at the same time as the gate of the transistor of the memoryelement itself, which reduces the number of steps required for thefabrication of the non-volatile memory element.

The robustness of a non-volatile memory element according to theinvention, during the recording of the binary value 1 using a powersupply voltage of around 7 V, or during later read operations of thestored binary value, may be further improved by using one or more of thefollowing additional features:

the second portion of the substrate, which corresponds to drift-fielddrain region, may have a concentration of n-type dopant species ofaround 5×10¹⁸ cm⁻³ (per cubic centimeter), over at least one part of thelength of this second portion in the longitudinal direction;

the first portion of the substrate, which corresponds to the secondelectrode of the capacitor, may have a concentration of n-type dopantspecies of around 5×10¹⁷ cm⁻³ within at least one part of the latter;

the transistor may comprise a gate isolation layer that has a thicknessgreater than or equal to the thickness of the insulating layer of thecapacitor, these thicknesses being measured in a direction perpendicularto the surface of the substrate;

the transistor may comprise a gate isolation layer that has a thicknessgreater than the thickness of the insulating layer of the capacitor, andthe second portion of the substrate, which corresponds to thedrift-field drain region, can have an identical doping, over at leastone part of the length of this portion in the longitudinal direction, tothat of an extension under the gate of the transistor of a third portionof the substrate corresponding to the source region of the transistor;

the substrate can comprise a fourth doped portion situated on one sideof the first portion corresponding to the second electrode of thecapacitor, which is opposite to the second portion of the substratecorresponding to the drift-field drain region, this fourth portionhaving an extension under the insulating layer of the capacitor that hasa doping identical to that of the said second portion of the substrate;

the fourth portion of the substrate can have a doping identical to thatof the third portion of the substrate which corresponds to the sourceregion of the transistor; and

the capacitor can be composed of several oblong capacitor sectionsdisposed on the surface of the substrate.

Some of these improvements contribute to reducing the electricalresistance of the capacitor which is apparent during the reading of thebinary value 1, after the insulating layer of the latter has beensubject to electrical breakdown. Heating of the memory element caused bythis electrical resistance is therefore reduced. In addition, the memoryelement exhibits an enhanced read contrast between the binary values 0and 1.

In addition, all these improvements can be obtained by adaptinglithographic masks already used in the fabrication of an integratedelectronic circuit of the MOS type. The additional cost of fabricationof an integrated electronic circuit which is generated by the formation,within this circuit, of a non-volatile memory element according to theinvention and/or according to these improvements is therefore small.

The invention also provides a process for the fabrication of anon-volatile memory element of the preceding type within an integratedelectronic circuit. According to this process, the second portion of thesubstrate, which corresponds to the drift-field drain region, isdetermined, during a doping step for this second portion, byself-alignment with respect to the gate of the transistor and to thefirst electrode of the capacitor parallel to the longitudinal direction.

The second portion of the substrate, corresponding to the drift-fielddrain region, could optionally be doped at the same time as extensionsof source and of drain regions of MOS transistors contained in thecircuit. In this way, the fabrication of a non-volatile memory elementaccording to the invention does not require the addition of specificprocess steps with respect to the MOS fabrication process for anintegrated electronic circuit.

Moreover, the fabrication of a non-volatile memory element according tothe invention may furthermore be combined with the MOS process accordingto the following improvements, taken separately or in combination:

the first electrode and the insulating layer of the capacitor can beformed at the same time as gates and gate isolation layers of MOStransistors contained within the circuit;

a part of the first portion of the substrate, which corresponds to thesecond electrode of the capacitor, can be doped at the same time asportions of the substrate that are designed to form the channels of MOStransistors contained in the circuit, for adjusting a threshold voltageof these transistors;

the second portion of the substrate, which corresponds to thedrift-field drain region, can be doped at the same time as extensions ofsource and of drain regions of MOS transistors contained in the circuit,and which have respective gate isolation layers that are thicker thanthe insulating layer of the capacitor;

the fourth portion of the substrate, which is situated on the side ofthe first portion corresponding to the second electrode of the capacitoropposite to the second portion of the substrate corresponding to thedrift-field drain region, can have an extension under the insulatinglayer of the capacitor, which is doped at the same time as the secondportion of the substrate;

the fourth portion of the substrate can be doped at the same time assource and drain regions of MOS transistors contained in the circuit;and

portions of a silicide material can be formed on the first electrode ofthe capacitor, on the gate and on the source region of the transistor,by using a resin mask that covers the substrate at least within a regionextending between this first electrode and this gate. Such a step forthe formation of portions of silicide on the contact regions of thecircuit already exists in the MOS circuit fabrication process, and theimprovement of the invention considered here resides in the design ofthe mask used for this step.

Lastly, an embodiment of the invention relates to an integratedelectronic circuit that comprises a non-volatile memory element such asis described hereinabove. This circuit can be a random access memoryarray, and the non-volatile memory element can be designed to allow arecovery programming of the random access memory array. Such aprogramming operation can allow, for example, defective parts of therandom access memory array to be neutralized and/or to be functionallyreplaced by other parts that are available and intended for thispurpose.

In accordance with an embodiment, an integrated electronic circuitcomprises a non-volatile memory element comprising a MOS transistorhaving a source in a substrate, a gate and a drain in the substrate withelectric field drift in a longitudinal direction. The circuit furthercomprises a capacitor having a first electrode is arranged on aninsulating layer and a second electrode comprising a first portion ofthe substrate located under the insulating layer and aligned with thedrain in the longitudinal direction. The electric field drift of thedrain is formed in a second portion of the substrate adjacent the firstportion and extending along the longitudinal direction from a firstextension underneath the gate of the transistor opposite the source to asecond extension underneath the insulating layer of the capacitor.

BRIEF DESCRIPTION OF THE DRAWINGS

Other characteristics and advantages of the invention will becomefurther apparent on reading the description which follows. The latter ispurely illustrative and should be read in conjunction with the appendeddrawings, in which:

FIG. 1 is a cross-sectional view of a non-volatile memory elementaccording to the invention; and

FIG. 2, which is established in correspondence with FIG. 1, is a topview of the non-volatile memory element on which are indicated maskboundaries used for the fabrication of the memory element.

DETAILED DESCRIPTION OF THE DRAWINGS

For reasons of clarity, the dimensions of the elements shown in thesefigures are not in proportion with their real dimensions or dimensionratios. Two directions, longitudinal and transverse, of the memoryelement are respectively denoted as L and T and are parallel to asurface S of a substantially planar integrated electronic circuitsubstrate used for fabricating the memory element. N is a directionperpendicular to the surface S and oriented upwards in FIG. 1. The terms‘on’, ‘under’, ‘lower’ and ‘upper’ are used in the following descriptionwith reference to this orientation. In addition, identical references inthe two figures denote identical elements.

Finally, the following will be limited to the description of asuccession of elementary fabrication steps for an integrated electroniccircuit of the MOS type, which allows the invention to be reproduced.Each elementary step, which is considered to be known per se, is notdescribed in detail.

The integrated electronic circuit substrate that is used for thefabrication of the non-volatile memory element, referenced 100 in FIG.1, is a P-type single-crystal silicon substrate. The substrate isresistive, having an electrical resistivity of around 10 to 15 Ω·cm(Ohm·centimetres) such as is widely used in 90 nm (nanometer) CMOStechnology. It is recalled that MOS technologies that have appearedsuccessively are characterized by the pitch of the lithographic masksused. Generally speaking, this pitch corresponds to the width of thegates of the MOS transistors that are fabricated according to thesetechnologies. By way of comparison with the concentrations of dopantspecies that are mentioned below, the substrate 100 has a concentrationof dopant species of the p type of around 10¹⁵ cm⁻³.

A ring of electrical isolation 102 is formed in the substrate 100 fromthe surface S. Such a ring can be, for example, of the STI (for ShallowTrench Isolation) type. It surrounds a portion of the substrate 100 thatwill contain the memory element. The region of the circuit correspondingto this useful portion of the substrate 100 is called active region andis referenced 101. For a non-volatile memory element according to theinvention, the surface area of the region 101 can be reduced to 3 μm²(square microns).

The fabrication process for MOS transistors of an integrated electroniccircuit usually comprises a first doping of the n type, which isdesigned to adjust threshold voltages of the MOS transistors of thecircuit. Such a doping is effected at the transistor locations with alow-energy implantation beam, such that the implanted dopant species areconfined just below the surface S of the substrate 100. For thenon-volatile memory element considered here, such a doping issimultaneously carried out in a portion of the active region 101 whichcorresponds to the capacitor, referenced 1 in FIG. 1. This portion,referenced 120, is defined by a lithography mask M1 which has an openingat this location (FIG. 2). The concentration of dopant species that isthus produced in the portion 120 is around 5×10¹⁷ cm⁻³. Such a doping ofthe portion 120 allows the residual electrical resistance of thecapacitor 1, after the insulating layer of the latter has been destroyedin order to record a binary value equal to 1, to be reduced.

Two MOS transistor gate structures are then formed on the surface S inthe active region 101. The first of these gate structures comprises aninsulating layer 13 overlaid by a conducting portion 14. The layer 13and the portion 14 are surrounded by an insulating spacer 15, parallelto the surface S. Similarly, the second gate structure comprises anelectrical isolation layer 23, a conducting portion 24 and a spacer 25.The layers 13 and 23 can be composed of silica (SiO₂), the conductingportions 14 and 24 of polysilicon and the spacers 15 and 25 of siliconnitride (Si₃N₄), for example. In a known technique, these two gatestructures are advantageously formed simultaneously by using a dedicatedlithography mask called a gate mask.

The insulating layer 13 and the conducting portion 14 will form thecapacitor 1 of the non-volatile memory element, with a portion 12 of thesubstrate 100 situated under the insulating layer 13. The portions 12and 14 form the two electrodes, lower and upper respectively, of thecapacitor 1. The conducting portion 24 and the layer 23 willrespectively form the gate and the gate isolation layer of thetransistor 2 of the non-volatile memory element.

Preferably, the insulating layer 13 of the capacitor 1 has a thicknesse1, measured in the direction N, which is less than the thickness e2 ofthe gate isolation layer 23 of the transistor 2. For example, e1 can beequal to 2.0 nm (nanometers) and e2 can be equal to 2.8 or 5.0 nm. Sucha difference between the thicknesses e1 and e2 contributes to preventingthe layer 23 from being damaged when a high voltage, for example of 7 V,is applied to the serial combination of the capacitor 1 and of thetransistor 2 for recording a binary value equal to 1. Indeed, because ofthis difference in thickness, the layer 13 is designed to break downelectrically before the layer 23.

A second doping of the substrate 100 is then performed in certainportions of the active region 101, referenced 11, 21 and 31. Thisdoping, of the n type, is effected by implantation of dopant speciesaccelerated in the direction N. The concentration of these species thatis reached in each of the portions of the substrate 11, 21 and 31 ishigh, for example of the order of 10²⁰ cm⁻³. This second doping is alsodesigned to form the source and the drain regions of the MOS transistorsof the circuit, other than the transistor 2 of the non-volatile memoryelement. Consequently, the doping of the portions 11, 21 and 31 does notrequire additional steps in the circuit fabrication process. It isobtained by adapting the lithography mask used for defining the sourceand drain regions of the transistors. This mask, referenced M2 in FIG.2, has two openings in the active region 101: the first opening extendson either side of the portion 14 of the capacitor 1, and the secondopening extends from the gate 24, on one side of the latter opposite tothe portion 14. In the directions L and T, the two openings of the maskM2 extend towards the outside of the active region 101 at least as faras the inside edges of the insulating portion 102. Overlays of theseopenings onto the portion 102 are included in order to adhere to thedesign rules relating to lithography masks.

For this second implantation, the gate structures of the capacitor 1 andof the transistor 2 form masks, such that portions 11, 21 and 31 areself-aligned relative to the upper electrode of the capacitor 1 and tothe gate of the transistor 2.

The portion 21 of the substrate 100 which is thus doped forms the sourceregion of the transistor 2.

The portions 11 and 31 are situated on either side of the portion of thesubstrate 100 that corresponds to the lower electrode 12 of thecapacitor 1. The portion 11, which is situated between the capacitor 1and one edge of the active region 101, is provided in order to avoid anedge of the upper electrode 14 being situated above the insulatingportion 102. A weakening of the portion 102 at the surface S, whichcould cause the non-volatile memory element to age more rapidly, is thusavoided.

The portion 31 forms a part of the drain 22 of the transistor 2. It issituated against the portion 12 and has an extension bounded in thedirection of the gate 14. For this purpose, an opaque part of the maskM2, which exists between the two openings of the latter, defines aportion of the substrate 100 within the active region 101 that remainsresistive, between the electrode 14 of the capacitor 1 and the gate 24of the transistor 2. This resistive portion, referenced 220 in FIG. 1,is designed to form an electric field drift region within the drainregion 22 of the transistor 2.

A third doping of the substrate 100, again of the n type, issubsequently performed within the whole of the active region 101, usingan implantation beam whose energy is lower than that of the implantationbeam used for the second doping. The implanted dopant species are nowtherefore contained within a thin film of the substrate 100, situatedunder the surface S, which has a smaller thickness than that of theportions 11, 21 and 31. This third implantation is also limited to theuncovered parts of the active region 101, outside of the structures inrelief of the electrode 14 of the capacitor 1 and of the gate 24 of thetransistor 2. In addition, the beam of dopant particles that is used forthis third implantation has a controlled divergence, such that dopantparticles are implanted obliquely into the substrate 100 under the edgesof the electrode 14 and of the gate 24. An extension 111 of the portion11 is thus formed, which prolongs the latter under one edge of theinsulating layer 13 and of the electrode 14 of the capacitor 1.Similarly, an extension 221 is simultaneously formed, which prolongs thesource region 21 under one edge of the insulating layer 23 and of thegate 24. These extensions 111 and 221 have a concentration of dopantspecies of 5×10¹⁸ cm^(—3). Such a value of concentration issubstantially identical to the doping level widely applied forextensions of an MOS (90 nm) transistor, when the thickness of the gateisolation layer is around 2.0 nm. In this way, the doping of theextensions 111 and 221 can be advantageously effected at the same timeas that of the extensions of the source and drain regions of the MOStransistors of the circuit which do not belong to the non-volatilememory element.

The portion 220 of the substrate 100 which is situated between theelectrode 14 and the gate 24 is simultaneously doped under identicalconditions. In particular, it has a concentration of dopant species ofthe n type that is also about 5×10¹⁸ cm⁻³. The resistivity of theportion 220 is thus adjusted in order to produce a suitable spreading ofthe electric field present between the electrode 14 and the gate 24. Inthis way, when a voltage of 7 V is applied between the electrode 14 andthe source 21, the current that flows through the memory element islimited by the electrical resistance of the portion 220. A protectionfor the transistor 1 is thus obtained against any damage to the latterthat could be caused by the current that flows through the memoryelement right after the breakdown of the insulating layer 13.

Thanks to the concentration of electrical carriers that is thus obtainedin the portion 220, the quantity of hot carriers generated in the memoryelement during operation of the latter is reduced, with respect to asituation according to which the portion 220 would be doped at the sametime as the MOS transistor source and drain regions. By hot carriers isunderstood high-energy electrons or holes that flow in the channel ofthe transistor 2, and which cause ageing of the transistor 2 byprogressively degrading the insulating layer 23 and the interface of thelatter with the substrate 100.

During the third doping process, a mask M3 can be formed on the circuitfor limiting the implantation of the dopant species to the relevantregions of the substrate 100. Given that the active region 101 issubject in its entirety to this implantation, the mask M3 has an openingthat comprises the whole of the region 101 (FIG. 2). Thus, the electricfield drift region 220 is bounded, by self-alignment, on the one hand bythe electrode 14 and by the gate 24 in the direction L, and on theother, by two opposing edges 101 a and 101 b of the active region 101 inthe direction T.

Given that the implantation beam used for this third doping isdivergent, dopant species are implanted into the substrate 100 under theedges of the electrode 14 and the gate 24 which bound the portion 220 byself-alignment. The portion 220 therefore has an extension, in thedirection L, that corresponds to an interval I slightly larger than theseparation distance between the gate 24 and the electrode 14.Nevertheless, the interval I is determined by the respective positionsof the gate 24 and of the electrode 14 on the surface S.

The inventors point out that the concentration of dopant species of5×10¹⁸ cm⁻³ that is produced in the extensions 111, 221 and in theportion 220 corresponds to a concentration value for extensions of anMOS transistor that has a gate thickness of 2.8 to 5.0 nm, for MOS (90nm) technology. In the embodiment described here, this concentrationvalue is also obtained in the substrate 100 on each side of theelectrode 12 of the capacitor 1, even though the thickness e1 of theinsulating layer 13 is only 2.0 nm. By way of comparison, for theextensions of a transistor that has a gate isolation layer of 2.0 nmthickness, the concentration of dopant species that is widely used is5×10¹⁹ cm⁻³.

Electrical contact regions are subsequently formed on the electrode 14,the gate 24 and the source region 21. The known technique ofsilicidation can be used, which consists in depositing portions of ametal, such as cobalt (Co), titanium (Ti) or nickel (Ni), selectively onthe electrode 14, the gate 24 and the source region 21. For thispurpose, a silicidation mask M4 is formed on the circuit, which coversthe regions of the latter that are not intended to receive metal.According to FIG. 2, the mask M4 covers a central part of the activeregion 101, included between the electrode 14 and the gate 24 in thedirection L. It could also cover the portion 11. A layer of metal isformed on the circuit in the openings of the mask M4. The mask M4 isthen dissolved, such that metal only remains on one part of theelectrode 14, one part of the gate 24 and on the source region 21. Thecircuit is then heated in order to cause a chemical reaction between themetal and the silicon material of the portions of the circuit with whichthe metal is in direct contact. Separate portions 160, 260 and 270 ofcobalt, titanium or nickel silicide are thus formed on the electrode 14,the gate 24 and the source region 21, respectively. These portions ofsilicide are designed to reduce electrical contact resistances appearingwhen electrical connections are later formed.

The fabrication of the electronic circuit is subsequently continued in aknown manner. A layer of silica 200 is formed on the substrate 100 ontop of the gate structures and the portions of silicide. Such a layer200 is called the interconnection layer. In particular, connections 16,26 and 27 are formed through the layer 200 in order to electricallyconnect the electrode 14 of the capacitor 1, together with the sourceregion 21 and the gate 24 of the transistor 1, via the portions ofsilicide 160, 260 and 270, respectively.

According to an improvement of the invention, the capacitor 1 has ashape designed to further reduce its electrical resistance, which isrelevant during a read step when the insulating layer 13 is electricallybroken down. For this purpose, the capacitor 1 is composed of severaloblong capacitor sections, forming for example a serpentine or a combstructure on the surface S, with a reduced width for each section.Typically, the width of at least some of the sections of the capacitor,measured in a direction parallel to the surface S, is less than tentimes the length, in this same direction, of an extension of the portion220 of the substrate under the insulating layer 13. In this way, theelectrode 12 of the capacitor 1 exhibits an apparent electricalconduction that is higher than that which would result from thresholdvoltage adjustment doping of the circuit MOS transistors alone. Areduced amount of heat is then produced within the capacitor during thereading of a binary value equal to 1. Indeed, the distance between thebreakdown point of the insulating layer of the capacitor and thedrift-field drain region is thus shortened. In addition, this results ina higher read contrast between stored binary values equal to 0 and 1.

A non-volatile memory element such as is described in detail hereinaboveis used by linking the connection 26 to a word line WLn and theconnection 27 to a bit line BLn.

In order to write the binary value 1 into the non-volatile memoryelement, the word line WLn and the bit line BLn have respective voltagesof 2.5 V and 0 V applied to them. Simultaneously, a voltage VDD of 7 Vis applied to the connection 16. The transistor 2 is then turned on,such that an electrical current flows in the capacitor 1, in the portion220 and the source region 21, which is sufficient to cause electricalbreakdown of the insulating layer 13. This current is limited by theohmic resistance of the portion 220 which corresponds to the electricfield drift region. It is limited to an intensity value such that thetransistor 2 is not damaged.

In order to later read the value written into the non-volatile memoryelement, the voltage VDD is set at the nominal operating value of theMOS circuit, in other words 2.5 V. When the memory element is selectedin order to read the binary value stored in the latter, potentials of2.0-2.5 V and 2.5 V are respectively applied to the bit line BL and tothe word line WL. The transistor 2 is then turned on and a read currentflows in the memory element if the stored binary value is 1. When thememory element is not selected, potentials of 2.5 V and 0 V arerespectively applied to the bit line BL and to the word line WL. Thetransistor 2 is then turned off, such that no read current flows throughthe memory element.

It will be understood that numerous modifications may be introduced intoa non-volatile memory element according to the invention, with respectto the embodiment that has been described in detail, while stillconserving at least some of the advantages presented. In particular, theinvention may be readily transposed to non-volatile memory elementsfabricated according to MOS technologies that correspond to differentgate widths.

Although preferred embodiments of the method and apparatus of thepresent invention have been illustrated in the accompanying Drawings anddescribed in the foregoing Detailed Description, it will be understoodthat the invention is not limited to the embodiments disclosed, but iscapable of numerous rearrangements, modifications and substitutionswithout departing from the spirit of the invention as set forth anddefined by the following claims.

1. An integrated electronic circuit comprising: a non-volatile memoryelement comprising a MOS transistor having a source in a substrate, agate and a drain in the substrate with electric field drift in alongitudinal direction, and further comprising a capacitor having afirst electrode is arranged on an insulating layer and a secondelectrode comprising a first portion of the substrate located under theinsulating layer and aligned with the drain in the longitudinaldirection, wherein the electric field drift of the drain is formed in asecond portion of the substrate adjacent the first portion and extendingalong the longitudinal direction from a first extension underneath thegate of the transistor opposite the source to a second extensionunderneath the insulating layer of the capacitor.
 2. The circuitaccording to claim 1, wherein the circuit is a random access memoryarray formed from a plurality of said non-volatile memory elements. 3.The circuit according to claim 1, wherein a doping of said secondportion is limited to a region substantially corresponding to a distancebetween the gate and the first electrode along the longitudinaldirection.
 4. The circuit according to claim 1, wherein the secondportion of the substrate corresponding to the electric field drift ofthe drain has a concentration of n-type dopant species of around 5×10¹⁸cm⁻³.
 5. The circuit according to claim 4, wherein the first portion ofthe substrate corresponding to the second electrode of the capacitor hasa concentration of n-type dopant species of around 5×10¹⁷ cm⁻³.
 6. Thecircuit according to claim 1, wherein the transistor comprises a gateisolation layer having a thickness greater than or equal to a thicknessof the insulating layer of the capacitor.
 7. The circuit according toclaim 1, wherein the second portion of the substrate corresponding tothe electric field drift of the drain has an identical doping to adoping of the first extension under the gate of the transistor.
 8. Thecircuit according to claim 1, wherein the second portion of thesubstrate corresponding to the electric field drift of the drain has anidentical doping to a doping of the second extension under theinsulating layer of the capacitor.
 9. The circuit according to claim 1,wherein the transistor and capacitor are formed in an active region ofthe substrate defined within an encircling isolation ring, the activeregion having a substrate surface area of less than 7 μm².
 10. Thecircuit according to claim 11, wherein the transistor and capacitor areformed in an active region of the substrate defined within an encirclingisolation ring, the active region having a substrate surface area ofless than 5 μm².
 11. The circuit according to claim 1, wherein thetransistor and capacitor are formed in an active region of the substratedefined within an encircling isolation ring, the active region having asubstrate surface area of about 3 μm².
 12. The circuit according toclaim 1, wherein second portion of the substrate forms a resistanceprotecting the transistor from damage during breakdown of the insulatinglayer of the capacitor to store a data value.
 13. A process for thefabrication of a non-volatile memory element, within an integratedelectronic circuit, for the storage of one bit, said memory elementcomprising a capacitor for recording a value of the bit by breakdown ofan insulating layer of said capacitor and a transistor for selectingsaid element, the transistor and the capacitor being formed within anactive region of an integrated electronic circuit substrate, wherein thetransistor is of the field-effect MOS type and incorporates a sourceregion designed to be connected to a first power supply terminal for thememory element, a gate designed to be connected to a selection terminalfor the memory element, and a drain region with electric field drift ina longitudinal direction, wherein the capacitor incorporates theinsulating layer arranged on top of a surface of the substrate, a firstelectrode of the capacitor is arranged on the insulating layer anddesigned to be connected to a second power supply terminal for thememory element, and a second electrode of the capacitor comprising afirst portion of the substrate located under the insulating layer and inline with the drain region of the transistor on a side opposite to thegate, the process comprising: providing the drift-field drain regionwithin the active region with a second portion of the substrate that isdetermined by self-alignment with respect to the gate and the firstelectrode parallel to the longitudinal direction, wherein providing isaccomplished during doping of said second portion of the substrate. 14.The process according to claim 13, further comprising doping the secondportion of the substrate corresponding to the drift-field drain regionat the same time as extensions of source and of drain regions of MOStransistors contained in the circuit.
 15. The process according to claim13, further comprising forming the first electrode and the insulatinglayer of the capacitor at the same time as gates and gate isolationlayers of MOS transistors contained in the circuit.
 16. The processaccording to claim 13, further comprising doping a part of the firstportion of the substrate corresponding to the second electrode of thecapacitor at the same time as portions of the substrate designed to formthe channels of MOS transistors contained in the circuit for adjusting athreshold voltage of said transistors.
 17. The process according toclaim 13, further comprising forming a gate isolation layer of thetransistor with a thickness e2 that is greater than or equal to athickness e1 of the insulating layer of the capacitor, said thicknessesbeing measured in a direction perpendicular to the surface of thesubstrate.
 18. The process according to claim 13, further comprisingdoping the second portion of the substrate corresponding to thedrift-field drain region at the same time as extensions of source and ofdrain regions of MOS transistors contained in the circuit, and formingrespective gate isolation layers that are thicker than the insulatinglayer of the capacitor, the thicknesses being measured in a direction(N) perpendicular to the surface of the substrate.
 19. The processaccording to claim 13, further comprising, with respect to a fourthportion of the substrate located on one side of the first portioncorresponding to the second electrode of the capacitor opposite to thesecond portion of the substrate corresponding to the drift-field drainregion, an extension under the insulating layer of the capacitor, saidextension being doped at the same time as the second portion of thesubstrate.
 20. The process according to claim 19, further comprisingdoping the fourth portion of the substrate at the same time as sourceand drain regions of MOS transistors contained within the circuit. 21.The process according to claim 13, further comprising forming portionsof a silicide material on the first electrode of the capacitor, on thegate and on the source region of the transistor, by using a maskcovering the substrate at least within a region extending between saidfirst electrode and said gate in the longitudinal direction.